T/F - C implicitly casts signed to unsigned for operations when one operand is signed and the other unsigned

T

How does sign extension work?

For unsigned, left is filled with 0s. For signed, repeat the most significant bit

When does overflow happen for unsigned?

x+y > 2^w -1

When does overflow happen for signed?

x+y < -2^w-1 or x+ y > 2^w-1 -1

Single precision has

32 bit

Double precision has

64 bit

Bias value for single precision

127

bias value for double precision

1023

Hidden bit is

the one in front of the decimal. Not used when calculating F because it will always be 1

Denormalized Value

Extremely small values close to 0 inclusive and can cause underflow

Normalized values

Values greater than largest denormalized value, small enough to fit into representation

Special values

+/- infinity or NaN

Data Storage

-Storing digital data in a form which balances considerations of cost, reliability and access speed - Uses state elements such as latches and flip flops -Uses logic (combinational/sequential)

Combinational logic

doesn't store state, current output based only on current input

Sequential Logic

clocked, has "memory"

Data Movement

moves data from one system to another using address and data buses

Data Transformation

Changes a given bit pattern with a related one - State elements store I/O -Combinational circuits perform transformation

32 bit systems use ____ words

4 byte

64 bit systems use ____ words

8 byte

MAR

Memory address register, puts address on an address bus

MDR

Memory data register, puts data on a data bus

Program Counter (PC)

holds address of current instruction (%rip) - will increment to point to next instruction

Instruction Register (IR)

Register where bits of instruction are saved so instruction can be executed

ALU

Arithmetic Logic Unit - combinational logic to implement all arithmetic and logical instructions, computes data/address values

Bus

electrical conduit used to carry bytes of info between hardware components (transfers words)

SRAM

Static RAM - each bit implemented w 6 transistor circuit -each bit retains current value/state indefinitely as long as it has power -resistant to electrical noise -faster access than DRAM -CPU cache

DRAM

Dynamic RAM - each bit stored on 1 capacitor/transistor -retains value for 10-100 milliseconds with power -modern CPU clock in nanosecond range -periodically refreshed every bit by reading and rewriting -susceptible to electrical noise -slower than SRAM

Volatile Memory

-loses info if supply voltage removed -RAM/caches

Non-Volatile Memory

- retains data when powered off - Flash/SSD/Tape/Disk Dries/EEPROM (Electrically erasable programmable ROM)

Memory Hierarchy

-builds memory subsystem with various levels of storage - storage at higher levels has faster access time but smaller size -storage at high level acts as a cache for storage below it

Caching

have smaller faster

Spatial Locality

-if a particular piece of data is accessed by a program, other data/instructions at nearby locations in memory are more likely to be accessed soon

Temporal Locality

-if a particular piece of data is accessed by a program, the same piece of data is likely to be accessed in the near future

Amdahl's Law

when we speed up one part of system, overall effect of performance depends upon how significant the part sped up is to the system and how big the increment was

ISA

Instruction Set Architecture - programmar visible interface such as instruction set, registers, memory organization, and exception handling

RISC

Reduced Instruction Set Computer architecture - found in smart phones/tablets - all instructions same length - ALU works on data in registers -only instructions affecting memory are loaded and stored - no condition registers -less power/heat -Higher # of registers

CISC

Complex Instruction Set Computer architecture - variable length encoding - move address words - ALU on registers or memory -Condition calls hold side effects of instructions -more power/heat generated

An x86-64 CPU has

-16 64 bit registers -program counter %rip floating point registers -words stored in little endian for THIS chip

What are rsp/rbp used for?

Stack management

Rsp

address of top of stack

Rbp

stack frame pointer, points to bottom of stack frame of function currently executing

rip holds

address of current/next instruction

ZF

Set if result of last ALU op is 0

SF

set if result of last ALU op resulted in sign bit of result being set

OF

set if result of last ALU op resulted in overflow for signed op

CF

set if result of last ALU op resulted in overflow for unsigned op

q

quad word - 64 bit

l

long word - 32 bit

w

word - 16 bit

b

byte - 8 bit

Immediate

CF

set if result of last ALU op resulted in overflow for unsigned op

q

quad word - 64 bit

l

long word - 32 bit

Normal (R)

Mem[Reg[R]] -movq (%rcx), %rax ram = *rcx

Displacement D(R)

Mem[Reg[R]+D] register R specifies start of memory region movq 8(%rbp), %rdx rex = *(rip + 8)

Imm (Rb, Ri, S)

Mem[Imm + Rg[Rb] + SRg[Ri]] Address = IM+Rb+Ri*S

Imm

constant displacement, can be any constant value

Rb

Base register

Ri

Index register

S

scale, only 1, 2, 4, 8

leaq

load effective address -dst must be an 8 byte register -src expressed by address mode expression -doesn't affect condition codes -computes address w/o memory reference -computes arithmetic expressers of x+ky+C

command for add in assembly

addX

command for subtract in assembly

subX

command for signed multiply in assembly

imulX

command for shift left in assembly

salX

command for ARITHMETIC shift right in assembly

sarX

command for LOGICAL shift right in assembly

shrX

exclusive or command in assembly

xorX

command for and in assembly

andX

command for or in assembly

orX

command for increment in assembly

incX

command for decrement in assembly

decX

command for negate in assembly

negX

command for not in assembly

notX

w

word - 16 bit

b

byte - 8 bit

Immediate

constant integer data denoted with $

Register

One of 16 integer registers

Memory

8 consecutive bytes of memory at address given by register (%rax) for example

Can you do memory to memory transfers with one instruction

NO